As it is well known, the development of the electric characteristics of the processors for PC, WORSTATION, and SERVER forces the constructors to search new solutions to meet the conditions required by the Computing Processing Units or CPUs.
In particular, the CPUs of the last generation require a high accuracy of the supply voltage, equal for example to 1.2 V+/−0.8% under steady state and 1.2 V+/−3% under transient conditions.
Beside these requests for accuracy, the used supply voltages may decrease also down to 1.1V and the load currents may increase up to 130 A with rise and fall times reaching 100 A/ms, with request for supply efficiency higher than 80%.
Suitable current or voltage regulator devices are able to ensure the required efficiency. A regulator suitable for the applications with a CPU includes, for example, a converter of the DC-DC interleaving type, used as an economic and efficient solution to meet the above needs realized by connecting in parallel N DC-DC converters in Buck or Step-down configuration, i.e., by connecting together their input and output terminals and driving them in an out-of-phase or interleaved way.
A similar converter of the DC-DC interleaving type is schematically shown in FIG. 1, globally indicated as regulator 1.
The regulator 1 includes a controller 2 coupled to a plurality of n buffers or phases 3 (multiphase configuration) including pairs of switches, so called high-side and low-side switches, driven by the controller 2 so as to supply a required power to a CPU 4 coupled to the output terminal OUT of the regulator 1.
The interleaving driving of the regulator 1 also implies that the controller 2 closes the high-side switches in the n phases with a phase shift equal to the switch period T divided by the number n of the phases.
A regulator 1 of the multiphase interleaving type is shown in greater detail in FIG. 2. In particular, the regulator 1 comprises n phases (indicated in the figure simply by their inductors L1 . . . Ln), each phase 3 comprising a high-side switch SWhs coupled in series with a low-side switch SWIs between a first and a second voltage reference, in particular an input voltage Vin and a ground GND.
Each phase 3 also comprises an inductor L inserted between a switch node X, or phase node, intermediate between the switches SWhs and SWIs. The regulator 1 also comprises an output capacitor Cout inserted between the output terminal OUT and the ground GND. Across the capacitor Cout there is an output voltage value Vout which is applied to the CPU 4.
The controller 2 supplies a driving signal of the PWM type for the high-side switches SWhs and low-side switches SWIs of the phases 3, sensitive to the level of the PWM signal, in particular the high-side switches being on and the low-side switches off respectively if PWM=1, vice versa the high-side switches being off and the low-side switches on if PWM=0. To do this, the controller 2 comprises a suitable modulator 5.
The current specifications that the processors require have been developed in time and during the last years have become more and more pressing and can be summarised in the underlying Table 1:
TABLE 12004A2004B2004C2005AIMAX 78A119A112A100AISTEP 55A 95A 89A 65AIstep/Trise 69A/ms119A/ms111A/ms217A/msIDCmin  5A  5A  5A  5AITDC 68A101A 96A 85AI_RISE800 nsec800 nsecTBD/04_A310 nsec2005B 2006A 2007AIMAX125A  65A  75AISTEP 95A  40A/60A   40A/60AIstep/Trise317A/ms1200A/ms2000A/msIDCmin  5A   5A   5AITDC115A  56A  56AI_RISE310 nsec  50 nsec  30 nsec
It is to be noted that the required increases of the maximum currents (IMAX) stopped in 2005 and a decrease thereof occurs in 2006, passing from about 125 A to 65 A. Such a decrease of the maximum current required leads towards designs of regulators using a smaller number of phases with respect to the regulators realized in the previous years.
In parallel, there occurred, however, a very high increase in the transient current rate of the processors (Istep/Trise), which may complicate a lot the design of the DC-DC interleaving converters: the rate value Istep/Trise raises in fact from 69 A/ms (value of 2004) to the value 1200 A/ms of 2006 up to 2000 A/μA in 2007.
In other words, the DC-DC interleaving converters of future generation are required to meet quicker and quicker load variations (so called Load Transients or LTs).
All this implies an increase in the costs of these converters for which increasing the number of output capacities Cout and thus the number n of phases of the converter itself may be necessary to respect the voltage tolerances as required.
In particular, if the number n of phases has been decided according to the efficiency requirements, to the temperature of the components (i.e., reliability), and to the power density, in the coming years the number of phases will be established also according to the required current transient specifications to be met.
Increasing the number of phases is a way for increasing the response speed of the converter.
For variations of currents equal to 70 A in a range of 50 ns for prior supplies, only by using an adequate number of ceramic capacities limiting the current loss of the processor in the first 50 ns of the load variation can these transients be met.
It is to be remembered in fact that a regulator has a band width proportional to n×Fsw, n being the number of phases of the regulator and Fsw the switching frequency of the same, in general about 300 KHz. The response times are then inversely proportional to the band (for example, for n=4 a response time of about 800 ns is obtained).
The regulator and its response speed can then heavily influence the manufacturing cost of the same and the number of electrolytic capacities to be used (which may influence the voltage loss of the processor for longer times than the ceramic capacities).
It is to be remarked that the band width and response speed of the regulator are, however, two indices which no longer operate for brief load variations such as 50 ns or even 30 ns, which can no longer be considered a deviation “of small signal” since the reaction times of the closed-loop system (i.e., the band width) may be greater at least of an order of magnitude.
Solutions proposed by the prior art aim at improving the response times of the controller without affecting its band width.
To do this, the controller is realized by means of a traditional control portion (sized according to the band width and to the Nyquist stability criterion) combined with a control portion of the non-linear type, which acts on the big signal any time a Load Transient LT is detected, as described for example in European patent applications No. EP 1 826 893 and EP 1 826 894, which are incorporated by reference.
A simplified example of this type of known controller is schematically shown in FIG. 3A, globally indicated with 10.
The controller 10 has an input terminal IN receiving an input voltage signal VID, or, more precisely, a regulation voltage being digitally programmed by the processor through digital lines called VID, and an output terminal OUT for its connection to a CPU (not shown since conventional), whereon an output voltage signal Vout is generated.
The controller 10 comprises in particular a first traditional control portion 11 and a second non-linear control portion 12, both coupled to an output stage 13, in turn coupled to the output terminal OUT of the controller 10. More in detail, as it will be clarified hereafter in the description, the second non-linear control portion 12 comprises a detector 14 of Load Transient LT with a corresponding clock signal, while the first traditional control portion 11 comprises a modulator 15 of the PWM type.
In detail, as shown in FIG. 3A, the input terminal IN is coupled, through a first resistor R1, to a first input terminal, in particular non-inverting (+), of a first operational amplifier OA1 of the first traditional control portion 11 having a second input terminal, in particular inverting (−) coupled through a second resistor R2 to a supply voltage reference GND as well as, in feedback through a third resistor R3, to an output terminal of the first operational amplifier OA1. A further fourth resistor R4 is coupled between the first input terminal of the first operational amplifier OA1 and an inner circuit node FBG.
The first traditional control portion 11 also comprises an error amplifier EA having a first input terminal, in particular inverting, coupled to an inner circuit node FB.
Furthermore, the inner circuit node FB is coupled to a second inner circuit node VDRP in turn coupled to a first current generator Gdroop suitable for supplying these nodes FB and VDRP, and thus the first input terminal of the error amplifier EA, with a current value Idroop equal to K*ITOT, K being a suitable scale factor and ITOT a total value of current which flows in the inductors of the phases of the converter to which the controller is 10 is coupled.
The inner circuit node FB is also coupled to an inner circuit node COMP in turn coupled to an output terminal of the error amplifier EA, in turn coupled to the modulator 15 of the PWM type.
The first traditional control portion 11 also comprises a first, a second and a third impedance block, ZF(s), ZFB(s) and ZLTB(s).
The first impedance block ZF(s) is inserted between the inner circuit node COMP and a common node Xz, this common node Xz being also coupled to the inner circuit nodes FB and VDRP. In particular, the first impedance block ZF(s) comprises a first capacitor CF and a resistor RF inserted, in series with each other, between the third inner circuit node COMP and the common node Xz, as well as a second capacitor CH inserted in parallel with and coupled between the inner circuit node COMP and the common node Xz.
The second impedance block ZFB(s) is inserted between an inner circuit node DIFFOUT and the common node Xz. In particular, this second impedance block ZFB(s) comprises a capacitor CFB and a resistor RFB inserted, in parallel with each other, between the inner circuit node DIFFOUT and the common node Xz. Furthermore, the second impedance block ZFB(s) is coupled to a first terminal T1 of the output stage 13.
The third impedance block ZLTB(s) is inserted between an inner circuit node LTB and the first terminal T1 of the output stage 13. In particular, this third impedance block ZLTB(s) comprises a capacitor CLTB and a resistor RLTB inserted, in series with each other, between the inner circuit node LTB and the first terminal T1 of the output stage 13.
The inner circuit node FBG is also coupled to a second terminal T2 of the output stage 13.
These inner circuit nodes, FB, VDRP, COMP, DIFFOUT, LTB and FBG, are coupled to a common line indicated with BUS in FIG. 3A.
The second non linear control portion 12 comprises in particular an operational amplifier OA2 having a first input terminal, in particular non inverting (+) coupled to the inner circuit node COMP of the first traditional control portion 11 and receiving therefrom a first voltage signal VCOMP, a second input terminal, in particular inverting (−), receiving a second ramp voltage signal LTB from the detector 14 of Load Transient LT and an output terminal coupled to a first input terminal of a logic gate PL of the OR type and supplying it with a PWM pulse indicated as PWM_BOOST. The logic gate PL also has a second input terminal coupled to an output terminal of the modulator 15 of the PWM type of the first traditional control portion 11 and receiving therefrom PWM pulses. The logic gate PL has an output terminal coupled to a third terminal T3 of the output stage 13.
In particular, the output stage 13 comprises an inductor L/N coupled to the third input terminal T3 and to the output terminal OUT of the controller 10, the series of a resistor ESR and of a capacitor C0 inserted between this output terminal OUT and a voltage reference, in particular a ground GND, as well as an output resistor R0 inserted between the output terminal OUT and the ground GND, ends of this output resistor R0 being coupled to the first and second terminals, T1 and T2.
Finally, the inner circuit node LTB is input coupled to the detector 14 of Load Transient LT of the second non linear control portion 12.
In this way, the application of a load is detected by the detector 14 of Load Transient LT, which substantially measures the derivative of the output voltage signal Vout. When this occurs, a pulse PWM_BOOST is created, shared by all the phases of the converter whereto the controller 10 is coupled, and of duration proportional to the decrease of the output voltage signal Vout, i.e., depending on the action of the first traditional control portion 11.
The action of the first traditional control portion 11 is then subjected to a first voltage signal VCOMP corrected by a balance control of the inductance currents (current sharing) of the converter phases whereto the controller 10 is coupled, as described in the above indicated patent applications.
In substance, the detector 14 of Load Transient LT zeroes the second ramp voltage signal LTB which, by comparison with the first voltage signal VCOMP, generates the PWM_BOOST pulse. The PWM_BOOST pulse is added, by the logic gate PL, in OR to the PWM pulses generated by the modulator 15 of the PWM type.
It is to be remembered that these PWM pulses are generated by the modulator 15 of the PWM type by comparing a control voltage value with a periodic clock signal with frequency Fsw. Normally, the clock signals of the PWM modulators have a triangular shape, this triangular shape being that for which a linear link exists at a first estimate between the voltage value of the control signal and the duty cycle of the generated square wave PWM.
The actions of the first traditional control portion 11 and of the second non-linear control portion 12 of the controller 10 realized according to the prior art are indicated in FIG. 3B by the broken arrow F1 and by the arrows F2 and F3, respectively, the control of the non-linear type acting on the big signal any time a Load Transient LT is detected.
Such a controller 10, like all the so called LTB systems, thus supplies a control action any time a load application or Load Transient LT occurs, thus in a synchronous way with the load frequency (normally indicated with Fload).
However, in applications like DC-DC switching converter, this controller has its own switch frequency, indicated as Fsw.
Thus the frame of the PWM pulses as supplied by the first traditional control portion 11, and in particular by the modulator 15 of the PWM type, which has the frequency Fsw, and those deriving from the second non-linear control portion 12 of the LTB type, which has the frequency Fload, are filtered by an output filter of the converter whereto the controller 10 is coupled and in particular by its output inductance and capacity Lo and Co, as schematically shown in FIG. 4A, where how the frame of PWM pulses reaches the output filter of the converter is shown.
Thus, by considering for example a multiphase converter with N=3 like in the example of FIG. 4A, the frame of the overall PWM pulses has an harmonic content which covers the frequency spectrum from the continuous up to high frequencies (which reproduce the square waves of the PWM pulses).
The output filter of such a converter, in particular a low-pass filter, offers a reduction of the width of these harmonics with a decrease of −40 dB/dec over the filter resonance (which occurs at the frequency FLC=½p sqrt(1/LeqCo) with Leq=Lo/N, N being the number of phases in the converter), as shown in FIG. 4B, where the transfer function of such an output filter is reported, together with the spectrum of the frame of PWM pulses received at the input, having frequency NFsw, equal to that of the output voltage signal Vout.
Thus the harmonics of the spectrum in the output voltage Vout, in the case of the multiphase topology with voltage loop, have content at the generic frequency:FAV+=N×FSW+KV×FLOAD FAV+>0 and where KV is a positive integer >1FAV−=N×FSW−KV×FLOAD FAV−>0 and where KV is a positive integer >1
Remembering that:                the current sharing control system, which serves to balance the currents in the converter phases, measures the current that flows in each single inductor of these phases and compares it with the mean current. A phase shift of the current of a phase from this mean current thus results in a smaller or greater duty cycle of a PWM pulse of this phase. The current sharing control system does not modify, the spectrum of the PWM pulses, which reach the output low-pass filter, but undergoes a stress at frequency equal to the load frequency Fload due to the reduced gain of such a control system and its reduced band width (about Fsw/5).        the control system of the current sharing observes input variables (the single currents of the inductances) which have, as main harmonic component, the switching frequency Fsw (and not NFsw like the output voltage signal Vout).        
The above condition becomes, if referred to the harmonics in the currents in the inductors, thus linked to the current sharing loop of the control for the balance of the currents:Facs+=Fsw+KCS×Fload Facs+>0 and where KCS is a positive integer >1Facs−=Fsw−KCS×Fload Facs−>0 and where KCS is a positive integer >1
It is immediately verified that the presence of the harmonic components FA+ and FA−, which refer to all the previously calculated harmonics (i.e., Fav+, Fav, Facs+, Facs−), has important consequences in the controller 10, both for the regulation system of the output voltage signal Vout and for the control system of the current sharing.
In particular, so as to persist in the converter, these harmonics do not have to be filtered neither by the regulation circuits of the output voltage signal Vout (which filters over frequencies equal to NFSW/10), nor by the control circuit of the current sharing which balances the currents in the inductances (which filters about at frequencies equal to FSW/5).
From these values of the cut off frequency of the regulation and control circuits, it is thus derived that the harmonic components FA+(always referred to the previously calculated harmonics, i.e., Fav+, Facs+) do not have any influence in the regulation circuit of the output voltage signal VOUT.
The same cannot be said for the harmonic components FA−, in turn referred to the previously calculated harmonics, i.e., Fav−, Facs−. In fact, it is immediately verified that the harmonics which fall down to low frequency remain in the converter comprising the above regulation and control circuits (which have gain) and then modify the value of the output voltage signal and the currents of the inductors of the converter phases. However only the harmonics FA−<FLC give a phase shift sensitive to the output voltage signal VOUT. The worst case is then constituted by the smaller FA− possible (not negative).
It is thus possible to calculate a limit value of the parameter KCSmax, like that value which supplies a minimum but positive harmonic FA−.
In particular, tests conducted, have shown that when the control system of the current sharing does not succeed in equalizing the currents in the N=3 inductors of the converter, beats are created in the output voltage value Vout and in the currents of the inductors themselves.
In the tested example, for KV=6 a harmonic FAV− is obtained at 24 KHz poorly filtered by the output low-pass filter with cut off frequency Flc. It has been verified that it is the control system of the current sharing that does not succeed in equalizing the currents in the N=3 inductors Lo, and for KCS=2 there are enormous excursions of the currents at 8 KHz.
These excursions or oscillations at frequencies equal to FAV and FACS, also indicated as beats, create thermal unbalances in the power components of the system which may seriously damage the converter.
Furthermore, it is to be noted that these beats may also be continuous. In this case, the control system of current sharing stops regulating and the currents of the inductances become statically different. This condition corresponds to FACS−=0 and is a very dangerous condition since it may damage the converter in a very short time.
It is also immediately verified that the converters without control by means of detector of Load Transient LT have their worst case of missed control of the currents of the inductances for KV=1.
This case KV=1 instead is not present when there is a control system through a detector of Load Transient LT since, for FLOAD=FSW, a frame of pulses PWM is obtained, strictly at frequency FLOAD and synchronous, for all the phases, as previously explained. By erasing the frame PWM at switching frequency FSW, beats at load frequency FLOAD are thus no longer possible, preventing any possible problem of current sharing.
This occurs since, further to the detection of the application of the load or Load Transient LT, the control action should pass from the first traditional control portion 11 to the second non-linear control portion 12. It thus inhibits for a masking time TMASK the passage of the PWM pulses. After the pulse PWM_BOOST in all the phases the passage of pulses PWM coming from the first traditional control portion 11 is inhibited again within the masking time TMASK to allow the recovery of the steady-state working conditions and to avoid an excessive consumption of energy, as schematically shown in FIG. 4C.
This technique, called “body-brake” or LTB_BRAKE, is used in case of release of the load itself and is described for example in the U.S. Pat. No. 6,806,689. A method for controlling a converter of the multiphase interleaving type which uses the body-brake technique provides that under release conditions of the load, all the high-side and low-side switches are turned off (while traditionally, i.e., in the case of controllers which do not use this body-brake technique, the controller would turn off the high-side switches but would turn on the low-side SWIs switches).
In this way the overshoot of the output voltage signal Vout further to the release of the load is widely decreased with respect to controllers which do not use this body-brake technique. In fact, the excess of charge dQ generated by the annulment of the currents of the inductors L of the phases of the multiphase interleaving converter is decreased thanks to the presence of turned off low-side switches.
For a masking time TMASK equal to 1/(NFSW), when TLOAD<TSW, a single pulse PWM_BOOST is present, equal to TLOAD/2<2TSW/N+VOUT/VCC×TLOAD i.e., at frequency FLOAD>0.5NFSW/(2+N*D) with D=VOUT/VCC 
For example, for FSW=300 KHz, VCC=12V, VOUT=1.4V, N=3, it is obtained that for FLOAD>200 KHz, the frame of the pulses PWM coincides only with the pulses PWM_BOOST, being composed only of pulses at FLOAD and thus, for FLOAD>200 KHz, beats cannot be present.
In substance, under conditions of applications of the load or load transient LT at high frequency, the multiphase converters have dangerous oscillations or beats of the currents in the phases, which may cause the increase of the electric and thermal stress of the power components comprised therein, negatively influencing the reliability of the converter as a whole.
In fact, during quick load transients, these devices are not only requested to regulate the voltage supplied, but also to control the currents of the single phases and their correct current sharing. As indicated above, this current sharing is well controlled for values of the load frequency Fload lower than the switching frequency FSW of the converter, while strong oscillations or beats of these currents are observed when the load frequency Fload gets near to the switching frequency FSW, these beats introducing additional electric stresses, for example in relation to the peak current of the power MOS transistors or to the magnetic saturation of the cores of the inductors.
It is also evident, as per what was explained above in relation to the solutions realized according to the prior art, that the introduction of a low-pass filter at the output of the converter does not eliminate these beats, in particular under the above-analyzed boundary-frequency conditions.